1. Field of the Invention
The present invention relates to a network system wherein a plurality of data stations connected to each other via two signal lines are provided so that the data transfer is mutually carried out between the respective data stations, and more particularly relates to the network system so constructed that a predetermined code string signal is supplied to each station via a synchronous signal line and a serial data on another data signal line is transferred to one of the other stations with a destination addressing to each station and transfer synchronization of data taken.
2. Description of the Prior Art
Two-wire network systems in which data strings and address signals are transmitted via their respective transmission lines have conventionally been proposed. In such systems, a predetermined code string signal is supplied via a synchronous signal transmission line to each station so as to provide addressing and synchronization (transmission control). This is exemplified by Japanese Patent Application Examined Open No. Sho. 52-13,367 titled to a system of signal multiplex transmission published on Apr. 14, 1977.
FIG. 1 shows one pair of transmission and reception stations 604, 605 disclosed in the above-identified document.
As shown in FIG. 1, a plurality of pairs of reception and transmission station 604 and 605 connected via a synchronous signal transmission line 602 and data transmission line 603. A synchronous signal transmission line 602 provides means for transmitting a synchronous signal as shown in FIG. 2(c) to each station from a synchronous signal generator 601.
The synchronous signal generator 601 generates an M series string code repeating such an order of "H", "H", "H", "L", "L", "H", and "L" at a regular interval T, as shown in FIG. 2(b), together with a clock signal having a constant interval .tau., as shown in FIG. 2(a), thus outputting the synchronous signal as shown in FIG. 2(c) after a pulsewidth modulation is performed.
The transmission station 604 comprises: (a) a reception circuit (REC.) 606 which receives the synchronous signal and demodulates it into the clock signal and series code signal as shown in FIGS. 2(a) and 2(c); (b) shift registers (S.R.) 607, 608, and 609 which supply sequentially the demodulated series code signal in synchronization with the clock signal; and (c) a logic circuit (LOG.) 610 which enables a gate 611 to open when a logic operation is carried out for mutual output signals of the three shift registers 607, 608, and 609 and the logic operation results in a predetermined logic output.
FIG. 3 shows the relationship between the output levels D1, D2, and D3 of the three shift registers 607, 608, and 609 shown in FIG. 1 and output signal X of the logic circuit 610 with respect to each period of the serially outputted clock signal shown in FIG. 2(a).
Seven kinds of combination patterns of the output logic signal levels L and H of the three shift registers 607, 608, and 609 appear over a period T of the code series signal, as shown in FIG. 3.
Hence, if one of the seven combination patterns in each transmission station 604 is a condition for establishing the logic operation result in the logic circuit 610 (for example, "H", "H", "L", as shown in FIG. 3, the gate 611 is opened when the logic of the logic circuit 610 is established once for the interval T of the series code signal. Consequently, one bit of data is sent to the data transmission line 603 from an output circuit 612 via the opened gate 111.
The reception station 605, on the other hand, comprises: (a) a reception circuit 613; (b) shift registers (S.R.) 614, 615, and 616; and (c) a logic circuit 617, these circuits being interconnected in the same way as the transmission station 604. A gate 618 is opened to connect the signal line 603 to an input circuit 619 only when the predetermined combination pattern is derived over the interval T of the series coded signal so that one bit of data is retrieved from the data transmission line 603 to the input circuit 619.
In this way, data transfer is established via the data transmission line 603 between a transmission station 604 having the logic circuit 610 which enables the gate 611 to open when a predetermined logic condition is established and a reception station 605 having the logic circuit 617 which enables the gate 618 to open when the same logic condition as the logic circuit 610 is established. In addition, the data can be transferred without mutual collision of data with a different synchronization taken for such transmission and reception stations having other predetermined patterns of logic conditions.
However, the conventional network system disclosed in the above-identified document has drawbacks as described below.
Since a time slot (a time corresponding to one clock period .tau. in the above example) for which a serial data string is transferred is fixed at a constant length of time, the time slot whose width in time is varied according to a length of data in the time slot cannot be set, thus a transmission speed of bit data needs to be increased in the time slot if a data length to be transmitted is long.
Therefore, the transmission efficiency is reduced in such a conventional network system and the network system becomes expensive if the high speed transmission of bit data is carried out.
In addition, a high-frequency noise radiation due to the high speed transmission of data causes the performance of an equipment used in such a conventional network system to be deteriorated. This results in a more expensive network system in order to reduce such a noise radiation.